OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_7seg.vhd] - Rev 294

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
284 Corrected the vhdl unit name and description for o8_7seg.vhd jshamlet 1425d 13h /open8_urisc/trunk/VHDL/o8_7seg.vhd
257 Fixed misnamed signal in o8_7seg.vhd and added a replacement switch interface that handles both static and pushbutton switches. jshamlet 1612d 23h /open8_urisc/trunk/VHDL/o8_7seg.vhd
244 Added two new generics to the CPU model. The first is a supervisory mode that disables the STP PSR_I instruction. This prevents errant code execution from setting the I bit, and disabling any subsequent memory protection logic. The second allows the default state of the I bit to be set at startup. If set true, initialization code will run with the I bit set, allowing it to bypass memory protection.

Also modified the RAM models to include write mask logic, where the mask register is write-protected by the I bit in the CPU. When enabled, the models will prevent code from writing to memory regions which do not have their mask bits set. The upshot is that code can effectively "write protect" the RAM - which is useful for multitasking applications.

Also, most modules have been updated with write qualification inputs, allowing a similar scheme to be used for I/O, though not as elegantly. I use a register module, whose own write qual line is attached to the external copy of the I bit as an I/O write protect register.

Lastly, added a new externally triggered timer, which can generate pulses with programmable delays and widths, and which can interrupt on either the input trigger, the output rising edge, or output falling edge. The time base can be either the internal microsecond tick signal, or an external clock.		 jshamlet 1633d 21h /open8_urisc/trunk/VHDL/o8_7seg.vhd
241 Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation. jshamlet 1645d 20h /open8_urisc/trunk/VHDL/o8_7seg.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.