| Rev |
Log message |
Author |
Age |
Path |
| 183 |
Renamed core to o8_cpu to match new naming scheme |
jshamlet |
1852d 23h |
/open8_urisc/trunk/VHDL/o8_cpu.vhd |
| 182 |
Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. |
jshamlet |
1852d 23h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 181 |
Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. |
jshamlet |
1853d 20h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 172 |
General code cleanup |
jshamlet |
3377d 21h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 169 |
Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. |
jshamlet |
3432d 22h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 168 |
Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component, |
jshamlet |
4211d 18h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 167 |
Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus. |
jshamlet |
4219d 17h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 164 |
Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. |
jshamlet |
4855d 12h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 162 |
Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. |
jshamlet |
4946d 05h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 156 |
Optimized for timing,
Flattened block structure to single entity. |
jshamlet |
5002d 20h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 155 |
Fixed additional interrupt logic bug,
Optimized several blocks - including ALU, stack, program counter, and data path. |
jshamlet |
5003d 15h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 154 |
Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed. |
jshamlet |
5008d 18h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 153 |
Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded,
Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered. |
jshamlet |
5035d 13h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 151 |
Fixed STO instruction and interrupt logic to avoid address bus corruption issues. |
jshamlet |
5045d 16h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 10 |
corrected implementation for BTT to match V8/ARClite definition, changed sense of reset, corrected comments to match source values |
khays |
5187d 01h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 8 |
Need to learn SVN... |
jshamlet |
5515d 12h |
/open8_urisc/trunk/VHDL/Open8.vhd |
| 7 |
Initial Upload |
jshamlet |
5515d 12h |
/open8_urisc/trunk/open8_urisc/VHDL/Open8.vhd |
