OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_epoch_timer.vhd] - Rev 209

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.		 jshamlet 1829d 06h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
194 Cleaned up licensing sections jshamlet 1837d 12h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1837d 13h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
189 Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals.		 jshamlet 1850d 11h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
184 More file/entity renaming to match private versions. jshamlet 1857d 12h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3382d 10h /open8_urisc/trunk/VHDL/o8_etc.vhd
172 General code cleanup jshamlet 3382d 10h /open8_urisc/trunk/VHDL/o8_etc.vhd
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3382d 11h /open8_urisc/trunk/VHDL/o8_etc.vhd
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3382d 11h /open8_urisc/trunk/VHDL/o8_etc.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.