OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_epoch_timer.vhd] - Rev 231

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
224 Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. jshamlet 1700d 07h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1701d 00h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
222 Created a modified version of the epoch timer with a 32-bit, 1-uS resolution timer/comparator. jshamlet 1701d 06h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
217 Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup.		 jshamlet 1702d 01h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
213 Code and comment cleanup jshamlet 1706d 02h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
212 Fixed issue with rewritten epoch timer not clearing alarm on set point write. jshamlet 1706d 08h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.		 jshamlet 1707d 21h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
194 Cleaned up licensing sections jshamlet 1716d 03h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1716d 04h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
189 Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals.		 jshamlet 1729d 02h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
184 More file/entity renaming to match private versions. jshamlet 1736d 03h /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3261d 01h /open8_urisc/trunk/VHDL/o8_etc.vhd
172 General code cleanup jshamlet 3261d 01h /open8_urisc/trunk/VHDL/o8_etc.vhd
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3261d 02h /open8_urisc/trunk/VHDL/o8_etc.vhd
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3261d 02h /open8_urisc/trunk/VHDL/o8_etc.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.