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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_gpout.vhd] - Rev 231

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224 Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. jshamlet 1700d 07h /open8_urisc/trunk/VHDL/o8_gpout.vhd
223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1701d 00h /open8_urisc/trunk/VHDL/o8_gpout.vhd
213 Code and comment cleanup jshamlet 1706d 02h /open8_urisc/trunk/VHDL/o8_gpout.vhd
194 Cleaned up licensing sections jshamlet 1716d 03h /open8_urisc/trunk/VHDL/o8_gpout.vhd
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1716d 04h /open8_urisc/trunk/VHDL/o8_gpout.vhd
172 General code cleanup jshamlet 3261d 02h /open8_urisc/trunk/VHDL/o8_gpout.vhd
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 4102d 21h /open8_urisc/trunk/VHDL/o8_gpout.vhd

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