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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_ram_4k.vhd] - Rev 236

Rev	Log message	Author	Age	Path
224	Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals.	jshamlet	1663d 19h	/open8_urisc/trunk/VHDL/o8_ram_4k.vhd
223	Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up.	jshamlet	1664d 13h	/open8_urisc/trunk/VHDL/o8_ram_4k.vhd
217	Broke out the vdsm8 as a separate entity, since it is used in several places, Even MORE code cleanup.	jshamlet	1665d 13h	/open8_urisc/trunk/VHDL/o8_ram_4k.vhd
209	Fixed an issue in the PIT timer that caused an immediate interrupt on interval write, Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register, While cleaning elsewhere, founding a spacing issue in the CPU HDL, Added a 4k ROM and MW core.	jshamlet	1671d 09h	/open8_urisc/trunk/VHDL/o8_ram_4k.vhd