URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_register.vhd] - Rev 223

Rev	Log message	Author	Age	Path
223	Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up.	jshamlet	1716d 03h	/open8_urisc/trunk/VHDL/o8_register.vhd
221	o8_vdsm8.vhd now has a default value assigned at compile time, o8_register.vhd was cleaned up some more.	jshamlet	1717d 03h	/open8_urisc/trunk/VHDL/o8_register.vhd
217	Broke out the vdsm8 as a separate entity, since it is used in several places, Even MORE code cleanup.	jshamlet	1717d 04h	/open8_urisc/trunk/VHDL/o8_register.vhd
213	Code and comment cleanup	jshamlet	1721d 05h	/open8_urisc/trunk/VHDL/o8_register.vhd
194	Cleaned up licensing sections	jshamlet	1731d 06h	/open8_urisc/trunk/VHDL/o8_register.vhd
191	Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays. Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.	jshamlet	1731d 06h	/open8_urisc/trunk/VHDL/o8_register.vhd
180	Added additional Open8 compatible modules	jshamlet	1756d 06h	/open8_urisc/trunk/VHDL/o8_register.vhd