OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rom_32k.vhd] - Rev 285

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
276 More comment fixes jshamlet 1489d 01h /open8_urisc/trunk/VHDL/o8_rom_32k.vhd
224 Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. jshamlet 1691d 07h /open8_urisc/trunk/VHDL/o8_rom_32k.vhd
223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1692d 00h /open8_urisc/trunk/VHDL/o8_rom_32k.vhd
217 Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup.		 jshamlet 1693d 01h /open8_urisc/trunk/VHDL/o8_rom_32k.vhd
194 Cleaned up licensing sections jshamlet 1707d 03h /open8_urisc/trunk/VHDL/o8_rom_32k.vhd
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1707d 03h /open8_urisc/trunk/VHDL/o8_rom_32k.vhd
174 Added ROM/RAM wrappers jshamlet 3252d 01h /open8_urisc/trunk/VHDL/o8_rom_32k.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.