URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rtc.vhd] - Rev 181

Rev	Log message	Author	Age	Path
177	Fixed comments in RTC module	jshamlet	2903d 00h	/open8_urisc/trunk/VHDL/o8_rtc.vhd
176	Fixed documentation errors, Modified uSec_Tick such that it is always generated regardless of the interval.	jshamlet	2907d 22h	/open8_urisc/trunk/VHDL/o8_rtc.vhd
172	General code cleanup	jshamlet	3102d 22h	/open8_urisc/trunk/VHDL/o8_rtc.vhd
168	Simplified write data path logic, Converted RTC to packed BCD, Corrected several bugs in real time clock component,	jshamlet	3936d 19h	/open8_urisc/trunk/VHDL/o8_rtc.vhd
167	Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow. Added several useful modules that use the Open8 bus.	jshamlet	3944d 17h	/open8_urisc/trunk/VHDL/o8_rtc.vhd