| Rev |
Log message |
Author |
Age |
Path |
| 223 |
Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. |
jshamlet |
1716d 03h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 217 |
Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup. |
jshamlet |
1717d 04h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 213 |
Code and comment cleanup |
jshamlet |
1721d 05h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 211 |
Ok, this time with feeling. Timer should now properly reset on interval update. |
jshamlet |
1722d 08h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 210 |
Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes. |
jshamlet |
1722d 11h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 209 |
Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core. |
jshamlet |
1723d 00h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 194 |
Cleaned up licensing sections |
jshamlet |
1731d 06h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 191 |
Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it. |
jshamlet |
1731d 06h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 190 |
Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00. |
jshamlet |
1743d 04h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 189 |
Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals. |
jshamlet |
1744d 04h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 177 |
Fixed comments in RTC module |
jshamlet |
3076d 07h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 176 |
Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval. |
jshamlet |
3081d 04h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 172 |
General code cleanup |
jshamlet |
3276d 04h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 168 |
Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component, |
jshamlet |
4110d 01h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
| 167 |
Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus. |
jshamlet |
4118d 00h |
/open8_urisc/trunk/VHDL/o8_rtc.vhd |
