URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Rev 205

Rev	Log message	Author	Age	Path
205	More code and comment cleanup for the new SDLC engine	jshamlet	1851d 01h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
204	Fixed more incorrect comments	jshamlet	1851d 02h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
202	Fixed receiver bug that caused false flag detection, Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.	jshamlet	1851d 09h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
201	Fixed comments regarding RX Checksum location	jshamlet	1853d 06h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
200	Renamed dual-port buffer to match other entities.	jshamlet	1853d 06h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
199	Added monitor ram for debugging and fixed issue with dual-port read path.	jshamlet	1853d 06h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
198	Removed debugging memory	jshamlet	1853d 14h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
196	Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored)	jshamlet	1853d 15h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
192	Added SDLC packet engine	jshamlet	1854d 11h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd