URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sys_timer.vhd] - Rev 188

Rev	Log message	Author	Age	Path
184	More file/entity renaming to match private versions.	jshamlet	1728d 20h	/open8_urisc/trunk/VHDL/o8_sys_timer.vhd
180	Added additional Open8 compatible modules	jshamlet	1733d 21h	/open8_urisc/trunk/VHDL/o8_pit.vhd
167	Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow. Added several useful modules that use the Open8 bus.	jshamlet	4095d 14h	/open8_urisc/trunk/VHDL/o8_pit.vhd