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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sys_timer.vhd] - Rev 223

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223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1716d 03h /open8_urisc/trunk/VHDL/o8_sys_timer.vhd
211 Ok, this time with feeling. Timer should now properly reset on interval update. jshamlet 1722d 09h /open8_urisc/trunk/VHDL/o8_sys_timer.vhd
210 Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes.		 jshamlet 1722d 11h /open8_urisc/trunk/VHDL/o8_sys_timer.vhd
194 Cleaned up licensing sections jshamlet 1731d 06h /open8_urisc/trunk/VHDL/o8_sys_timer.vhd
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1731d 07h /open8_urisc/trunk/VHDL/o8_sys_timer.vhd
189 Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals.		 jshamlet 1744d 05h /open8_urisc/trunk/VHDL/o8_sys_timer.vhd
184 More file/entity renaming to match private versions. jshamlet 1751d 06h /open8_urisc/trunk/VHDL/o8_sys_timer.vhd
180 Added additional Open8 compatible modules jshamlet 1756d 07h /open8_urisc/trunk/VHDL/o8_pit.vhd
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 4118d 00h /open8_urisc/trunk/VHDL/o8_pit.vhd

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