| Rev |
Log message |
Author |
Age |
Path |
| 244 |
Added two new generics to the CPU model. The first is a supervisory mode that disables the STP PSR_I instruction. This prevents errant code execution from setting the I bit, and disabling any subsequent memory protection logic. The second allows the default state of the I bit to be set at startup. If set true, initialization code will run with the I bit set, allowing it to bypass memory protection.
Also modified the RAM models to include write mask logic, where the mask register is write-protected by the I bit in the CPU. When enabled, the models will prevent code from writing to memory regions which do not have their mask bits set. The upshot is that code can effectively "write protect" the RAM - which is useful for multitasking applications.
Also, most modules have been updated with write qualification inputs, allowing a similar scheme to be used for I/O, though not as elegantly. I use a register module, whose own write qual line is attached to the external copy of the I bit as an I/O write protect register.
Lastly, added a new externally triggered timer, which can generate pulses with programmable delays and widths, and which can interrupt on either the input trigger, the output rising edge, or output falling edge. The time base can be either the internal microsecond tick signal, or an external clock. |
jshamlet |
1680d 21h |
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd |
| 242 |
Added write protect logic to the RAM cores and system timer as part of scheme to keep tasks from messing up the scheduler or other task's memory. The RAM is now divided into regions with a separate write mask register. The write mask register itself is only writeable with the I bit is set (during an interrupt or by setting it using STP PSR_I). The 1K memory is divided into 16, 64 byte regions while the 4K memory is divided into 32, 128 byte regions. The system timer simply checks for the I bit being set when the write protect generic is set.
Note that setting the write_protect generic false, or leaving it unset, will keep the previous behavior. |
jshamlet |
1688d 01h |
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd |
| 229 |
Created a new version of the system timer with 24-bit, 1-uS resolution. The new timer has a much different register interface, so it is now o8_sys_timer_ii. |
jshamlet |
1714d 01h |
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd |
| 224 |
Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. |
jshamlet |
1715d 04h |
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd |
| 223 |
Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. |
jshamlet |
1715d 21h |
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd |
| 211 |
Ok, this time with feeling. Timer should now properly reset on interval update. |
jshamlet |
1722d 02h |
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd |
| 210 |
Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes. |
jshamlet |
1722d 05h |
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd |
| 194 |
Cleaned up licensing sections |
jshamlet |
1730d 23h |
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd |
| 191 |
Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it. |
jshamlet |
1731d 00h |
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd |
| 189 |
Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals. |
jshamlet |
1743d 22h |
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd |
| 184 |
More file/entity renaming to match private versions. |
jshamlet |
1751d 00h |
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd |
| 180 |
Added additional Open8 compatible modules |
jshamlet |
1756d 00h |
/open8_urisc/trunk/VHDL/o8_pit.vhd |
| 167 |
Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus. |
jshamlet |
4117d 17h |
/open8_urisc/trunk/VHDL/o8_pit.vhd |
