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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_trig_delay.vhd] - Rev 297

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Rev Log message Author Age Path
292 Updated the o8_trig_delay entity by:
1) Added a global interrupt enable,
2) Added the ability to trigger on both the pre- and post-arm trigger input
3) Added the ability to read the external input on offset 7		 jshamlet 1266d 05h /open8_urisc/trunk/VHDL/o8_trig_delay.vhd
275 Fixed a minor comment error. jshamlet 1490d 19h /open8_urisc/trunk/VHDL/o8_trig_delay.vhd
274 Updated comments with more corrections jshamlet 1491d 02h /open8_urisc/trunk/VHDL/o8_trig_delay.vhd
244 Added two new generics to the CPU model. The first is a supervisory mode that disables the STP PSR_I instruction. This prevents errant code execution from setting the I bit, and disabling any subsequent memory protection logic. The second allows the default state of the I bit to be set at startup. If set true, initialization code will run with the I bit set, allowing it to bypass memory protection.

Also modified the RAM models to include write mask logic, where the mask register is write-protected by the I bit in the CPU. When enabled, the models will prevent code from writing to memory regions which do not have their mask bits set. The upshot is that code can effectively "write protect" the RAM - which is useful for multitasking applications.

Also, most modules have been updated with write qualification inputs, allowing a similar scheme to be used for I/O, though not as elegantly. I use a register module, whose own write qual line is attached to the external copy of the I bit as an I/O write protect register.

Lastly, added a new externally triggered timer, which can generate pulses with programmable delays and widths, and which can interrupt on either the input trigger, the output rising edge, or output falling edge. The time base can be either the internal microsecond tick signal, or an external clock.		 jshamlet 1657d 00h /open8_urisc/trunk/VHDL/o8_trig_delay.vhd

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