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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vector_rx.vhd] - Rev 267

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247 Fixed problem where parallel interface was always forcing the data registers due to bad alias. jshamlet 1662d 08h /open8_urisc/trunk/VHDL/o8_vector_rx.vhd
246 The system timer module now allows for an optional millisecond resolution (settable through a generic). This prescalar enable permits the timer to operate from 1 to 256 mS, which is useful for a variety of tasks, such as serial timeouts and watchdog timers. The enable is not software settable, as this would complicate the register interface and isn't generally useful in an HDL based SOC design.

The vector interface now has a parallel interface that runs beside the serial interface, and is useful for connecting to DIO cards or other parallel interfaces.		 jshamlet 1662d 13h /open8_urisc/trunk/VHDL/o8_vector_rx.vhd
244 Added two new generics to the CPU model. The first is a supervisory mode that disables the STP PSR_I instruction. This prevents errant code execution from setting the I bit, and disabling any subsequent memory protection logic. The second allows the default state of the I bit to be set at startup. If set true, initialization code will run with the I bit set, allowing it to bypass memory protection.

Also modified the RAM models to include write mask logic, where the mask register is write-protected by the I bit in the CPU. When enabled, the models will prevent code from writing to memory regions which do not have their mask bits set. The upshot is that code can effectively "write protect" the RAM - which is useful for multitasking applications.

Also, most modules have been updated with write qualification inputs, allowing a similar scheme to be used for I/O, though not as elegantly. I use a register module, whose own write qual line is attached to the external copy of the I bit as an I/O write protect register.

Lastly, added a new externally triggered timer, which can generate pulses with programmable delays and widths, and which can interrupt on either the input trigger, the output rising edge, or output falling edge. The time base can be either the internal microsecond tick signal, or an external clock.		 jshamlet 1665d 09h /open8_urisc/trunk/VHDL/o8_vector_rx.vhd
240 Simplified the vector tx/rx system to a single line. An idle detector replaces the attn_req signal. jshamlet 1679d 12h /open8_urisc/trunk/VHDL/o8_vector_rx.vhd

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