URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [sdlc_dp512b_ram.vhd] - Rev 265

Rev	Log message	Author	Age	Path
200	Renamed dual-port buffer to match other entities.	jshamlet	1730d 01h	/open8_urisc/trunk/VHDL/sdlc_dp512b_ram.vhd
195	Added dual-port RAM core for SDLC interface.	jshamlet	1731d 05h	/open8_urisc/trunk/VHDL/ram_dp512b_core.vhd