URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [Makefile] - Rev 42

Rev	Log message	Author	Age	Path
33	Fixed the network receive CRC and MAC checking, and added ip-checking and minimum packet length checking to the receiver.	dgisselq	3118d 09h	/openarty/trunk/rtl/Makefile
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	3120d 05h	/openarty/trunk/rtl/Makefile
25	The memory now works. However, the core speed has been lowered to 81.25MHz to do this. The top level file is no longer fasttop.v, but toplevel.v.	dgisselq	3156d 10h	/openarty/trunk/rtl/Makefile
12	A work in progress. This checkin contains fixes for the flash (mostly), together with some logic reductions facilitating full speed (200MHz) build.	dgisselq	3188d 08h	/openarty/trunk/rtl/Makefile
3	Initial set of files. The flash appears to work, memory hasn't been started, the MDIO controller works in simulation, etc. Everything below fasttop.v works at 200MHz (not the CPU---yet).	dgisselq	3203d 12h	/openarty/trunk/rtl/Makefile