URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [builddate.v] - Rev 34

Rev	Log message	Author	Age	Path
34	These updates bring the distribution along to the point where both the GPS clock subsecond tracking, as well as the OLEDrgb controller now work.	dgisselq	2995d 13h	/openarty/trunk/rtl/builddate.v
33	Fixed the network receive CRC and MAC checking, and added ip-checking and minimum packet length checking to the receiver.	dgisselq	3000d 19h	/openarty/trunk/rtl/builddate.v
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	3002d 14h	/openarty/trunk/rtl/builddate.v
25	The memory now works. However, the core speed has been lowered to 81.25MHz to do this. The top level file is no longer fasttop.v, but toplevel.v.	dgisselq	3038d 19h	/openarty/trunk/rtl/builddate.v
13	Here are the updates necessary to get the initial Quad SPI flash driver working. This includes in particular the bus interconnect (in fastmaster.v), and the final hookup to the external wires (in fasttop.v).	dgisselq	3069d 15h	/openarty/trunk/rtl/builddate.v
12	A work in progress. This checkin contains fixes for the flash (mostly), together with some logic reductions facilitating full speed (200MHz) build.	dgisselq	3070d 18h	/openarty/trunk/rtl/builddate.v
3	Initial set of files. The flash appears to work, memory hasn't been started, the MDIO controller works in simulation, etc. Everything below fasttop.v works at 200MHz (not the CPU---yet).	dgisselq	3085d 22h	/openarty/trunk/rtl/builddate.v