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[/] [openarty/] [trunk/] [rtl/] [builddate.v] - Rev 57

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50 Updated the CPU and distribution in general to handle 8-bit bytes. dgisselq 2781d 23h /openarty/trunk/rtl/builddate.v
49 Moved the location of the ZIPSYSTEM in memory, made the artyboard.h constants
more friendly and more complete, fixed two bugs in the CPU (jumps to breaks,
and s/w clearing of icache), added a NO_USERMODE option to the CPU, and more.
Rebuild any user programs before using this build.		 dgisselq 2906d 12h /openarty/trunk/rtl/builddate.v
44 Fixed the flash so that it now runs in 1) high speed (41MHz), and 2) that it
doesn't struggle to do read bursts. This should greatly speed up access time.		 dgisselq 2926d 16h /openarty/trunk/rtl/builddate.v
36 Lots of changes, see the git changelog for details. dgisselq 2933d 01h /openarty/trunk/rtl/builddate.v
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2936d 15h /openarty/trunk/rtl/builddate.v
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2941d 21h /openarty/trunk/rtl/builddate.v
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2943d 16h /openarty/trunk/rtl/builddate.v
25 The memory now works. However, the core speed has been lowered to 81.25MHz
to do this. The top level file is no longer fasttop.v, but toplevel.v.		 dgisselq 2979d 21h /openarty/trunk/rtl/builddate.v
13 Here are the updates necessary to get the initial Quad SPI flash driver working.
This includes in particular the bus interconnect (in fastmaster.v), and the
final hookup to the external wires (in fasttop.v).		 dgisselq 3010d 17h /openarty/trunk/rtl/builddate.v
12 A work in progress. This checkin contains fixes for the flash (mostly),
together with some logic reductions facilitating full speed (200MHz) build.		 dgisselq 3011d 20h /openarty/trunk/rtl/builddate.v
3 Initial set of files. The flash appears to work, memory hasn't been started,
the MDIO controller works in simulation, etc. Everything below fasttop.v works
at 200MHz (not the CPU---yet).		 dgisselq 3027d 00h /openarty/trunk/rtl/builddate.v

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