URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [fasttop.v] - Rev 38

Rev	Log message	Author	Age	Path
25	The memory now works. However, the core speed has been lowered to 81.25MHz to do this. The top level file is no longer fasttop.v, but toplevel.v.	dgisselq	2981d 12h	/openarty/trunk/rtl/fasttop.v
24	Here are the updates from the first (failed) attempt to try to integrate the DDR3 SDRAM controller onto this board.	dgisselq	3000d 08h	/openarty/trunk/rtl/fasttop.v
13	Here are the updates necessary to get the initial Quad SPI flash driver working. This includes in particular the bus interconnect (in fastmaster.v), and the final hookup to the external wires (in fasttop.v).	dgisselq	3012d 08h	/openarty/trunk/rtl/fasttop.v
12	A work in progress. This checkin contains fixes for the flash (mostly), together with some logic reductions facilitating full speed (200MHz) build.	dgisselq	3013d 10h	/openarty/trunk/rtl/fasttop.v
3	Initial set of files. The flash appears to work, memory hasn't been started, the MDIO controller works in simulation, etc. Everything below fasttop.v works at 200MHz (not the CPU---yet).	dgisselq	3028d 14h	/openarty/trunk/rtl/fasttop.v