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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [msp_debug.v] - Rev 105

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103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 5014d 13h /openmsp430/trunk/core/bench/verilog/msp_debug.v
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim
olivier.girard 5023d 07h /openmsp430/trunk/core/bench/verilog/msp_debug.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).
olivier.girard 5566d 11h /openmsp430/trunk/core/bench/verilog/msp_debug.v
17 Updated header with SVN info olivier.girard 5592d 07h /openmsp430/trunk/core/bench/verilog/msp_debug.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5627d 06h /openmsp430/trunk/core/bench/verilog/msp_debug.v

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