URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [msp_debug.v] - Rev 106

Rev	Log message	Author	Age	Path
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	4992d 07h	/openmsp430/trunk/core/bench/verilog/msp_debug.v
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	5001d 01h	/openmsp430/trunk/core/bench/verilog/msp_debug.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5544d 05h	/openmsp430/trunk/core/bench/verilog/msp_debug.v
17	Updated header with SVN info	olivier.girard	5570d 01h	/openmsp430/trunk/core/bench/verilog/msp_debug.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5605d 01h	/openmsp430/trunk/core/bench/verilog/msp_debug.v