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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [msp_debug.v] - Rev 188

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134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4634d 17h /openmsp430/trunk/core/bench/verilog/msp_debug.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4941d 17h /openmsp430/trunk/core/bench/verilog/msp_debug.v
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 5017d 23h /openmsp430/trunk/core/bench/verilog/msp_debug.v
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 5026d 17h /openmsp430/trunk/core/bench/verilog/msp_debug.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5569d 21h /openmsp430/trunk/core/bench/verilog/msp_debug.v
17 Updated header with SVN info olivier.girard 5595d 16h /openmsp430/trunk/core/bench/verilog/msp_debug.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5630d 16h /openmsp430/trunk/core/bench/verilog/msp_debug.v

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