URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [ram.v] - Rev 106

Rev	Log message	Author	Age	Path
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	5014d 05h	/openmsp430/trunk/core/bench/verilog/ram.v
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	5054d 23h	/openmsp430/trunk/core/bench/verilog/ram.v
72	Expand configurability options of the program and data memory sizes.	olivier.girard	5230d 00h	/openmsp430/trunk/core/bench/verilog/ram.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5566d 03h	/openmsp430/trunk/core/bench/verilog/ram.v
17	Updated header with SVN info	olivier.girard	5591d 22h	/openmsp430/trunk/core/bench/verilog/ram.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5626d 22h	/openmsp430/trunk/core/bench/verilog/ram.v