URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [registers.v] - Rev 208

Rev	Log message	Author	Age	Path
145	Add Dhrystone and CoreMark benchmarks to the simulation environment.	olivier.girard	4566d 08h	/openmsp430/trunk/core/bench/verilog/registers.v
134	Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.	olivier.girard	4635d 08h	/openmsp430/trunk/core/bench/verilog/registers.v
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	5027d 08h	/openmsp430/trunk/core/bench/verilog/registers.v
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	5125d 08h	/openmsp430/trunk/core/bench/verilog/registers.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5449d 11h	/openmsp430/trunk/core/bench/verilog/registers.v
17	Updated header with SVN info	olivier.girard	5596d 08h	/openmsp430/trunk/core/bench/verilog/registers.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5631d 08h	/openmsp430/trunk/core/bench/verilog/registers.v