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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [tb_openMSP430.v] - Rev 79

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72 Expand configurability options of the program and data memory sizes. olivier.girard 5230d 12h /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
67 Added 16x16 Hardware Multiplier. olivier.girard 5377d 19h /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5388d 09h /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5416d 13h /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5445d 12h /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5445d 13h /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5566d 14h /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
17 Updated header with SVN info olivier.girard 5592d 10h /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5627d 10h /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v

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