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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_alu.v] - Rev 105

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103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 5147d 00h /openmsp430/trunk/core/rtl/verilog/omsp_alu.v
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 5147d 18h /openmsp430/trunk/core/rtl/verilog/omsp_alu.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5577d 19h /openmsp430/trunk/core/rtl/verilog/omsp_alu.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5577d 20h /openmsp430/trunk/core/rtl/verilog/alu.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5698d 22h /openmsp430/trunk/core/rtl/verilog/alu.v
17 Updated header with SVN info olivier.girard 5724d 17h /openmsp430/trunk/core/rtl/verilog/alu.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5759d 17h /openmsp430/trunk/core/rtl/verilog/alu.v

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