| Rev |
Log message |
Author |
Age |
Path |
| 205 |
Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools). |
olivier.girard |
3507d 18h |
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v |
| 202 |
Add DMA interface support + LINT cleanup |
olivier.girard |
3521d 18h |
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v |
| 180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4377d 17h |
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4717d 18h |
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v |
| 117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4990d 19h |
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
5024d 18h |
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
5080d 17h |
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
5101d 00h |
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v |
| 85 |
Diverse RTL cosmetic updates. |
olivier.girard |
5136d 18h |
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v |
| 34 |
To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. |
olivier.girard |
5531d 20h |
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v |
| 33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5531d 20h |
/openmsp430/trunk/core/rtl/verilog/clock_module.v |
| 23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5652d 22h |
/openmsp430/trunk/core/rtl/verilog/clock_module.v |
| 17 |
Updated header with SVN info |
olivier.girard |
5678d 17h |
/openmsp430/trunk/core/rtl/verilog/clock_module.v |
| 2 |
Upload complete openMSP430 project to the SVN repository |
olivier.girard |
5713d 17h |
/openmsp430/trunk/core/rtl/verilog/clock_module.v |
