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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_clock_module.v] - Rev 153

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134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4718d 20h /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4991d 21h /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 5025d 20h /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 5081d 19h /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 5102d 02h /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
85 Diverse RTL cosmetic updates. olivier.girard 5137d 20h /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5532d 22h /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5532d 22h /openmsp430/trunk/core/rtl/verilog/clock_module.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5654d 00h /openmsp430/trunk/core/rtl/verilog/clock_module.v
17 Updated header with SVN info olivier.girard 5679d 20h /openmsp430/trunk/core/rtl/verilog/clock_module.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5714d 19h /openmsp430/trunk/core/rtl/verilog/clock_module.v

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