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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_dbg.v] - Rev 180

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175 Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports.
olivier.girard 4317d 03h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4424d 04h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)
olivier.girard 4512d 04h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 4631d 04h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4904d 05h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4938d 04h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 4994d 02h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 5014d 10h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
85 Diverse RTL cosmetic updates. olivier.girard 5050d 03h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.
olivier.girard 5055d 04h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.
olivier.girard 5203d 05h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
53 Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)

Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch.
olivier.girard 5416d 06h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5445d 05h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.
olivier.girard 5445d 06h /openmsp430/trunk/core/rtl/verilog/dbg.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).
olivier.girard 5566d 08h /openmsp430/trunk/core/rtl/verilog/dbg.v
17 Updated header with SVN info olivier.girard 5592d 03h /openmsp430/trunk/core/rtl/verilog/dbg.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5627d 03h /openmsp430/trunk/core/rtl/verilog/dbg.v

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