OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_dbg.v] - Rev 91

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
85 Diverse RTL cosmetic updates. olivier.girard 5053d 16h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 5058d 17h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5206d 17h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
53 Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)

Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch.		 olivier.girard 5419d 19h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5448d 18h /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5448d 19h /openmsp430/trunk/core/rtl/verilog/dbg.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5569d 21h /openmsp430/trunk/core/rtl/verilog/dbg.v
17 Updated header with SVN info olivier.girard 5595d 16h /openmsp430/trunk/core/rtl/verilog/dbg.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5630d 16h /openmsp430/trunk/core/rtl/verilog/dbg.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.