URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_dbg_uart.v] - Rev 84

Rev	Log message	Author	Age	Path
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5203d 01h	/openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
34	To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.	olivier.girard	5445d 02h	/openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5445d 03h	/openmsp430/trunk/core/rtl/verilog/dbg_uart.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5566d 04h	/openmsp430/trunk/core/rtl/verilog/dbg_uart.v
17	Updated header with SVN info	olivier.girard	5592d 00h	/openmsp430/trunk/core/rtl/verilog/dbg_uart.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5627d 00h	/openmsp430/trunk/core/rtl/verilog/dbg_uart.v