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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_frontend.v] - Rev 93

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91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 5027d 11h /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
85 Diverse RTL cosmetic updates. olivier.girard 5050d 10h /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
60 Cleanup of the PC (R0) generation logic.
Formal equivalence was shown between the new and old code with Synopsys' Formality (to make sure that nothing has been broken :-P ).		 olivier.girard 5409d 10h /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
53 Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)

Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch.		 olivier.girard 5416d 13h /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5445d 12h /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5445d 13h /openmsp430/trunk/core/rtl/verilog/frontend.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5566d 14h /openmsp430/trunk/core/rtl/verilog/frontend.v
17 Updated header with SVN info olivier.girard 5592d 10h /openmsp430/trunk/core/rtl/verilog/frontend.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5627d 10h /openmsp430/trunk/core/rtl/verilog/frontend.v

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