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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_register_file.v] - Rev 167

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134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4610d 04h /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
132 Update FPGA examples with the POP.B bug fix olivier.girard 4623d 04h /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4631d 03h /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4883d 05h /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4917d 04h /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4993d 10h /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5424d 05h /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5424d 06h /openmsp430/trunk/core/rtl/verilog/register_file.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5545d 08h /openmsp430/trunk/core/rtl/verilog/register_file.v
17 Updated header with SVN info olivier.girard 5571d 03h /openmsp430/trunk/core/rtl/verilog/register_file.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5606d 03h /openmsp430/trunk/core/rtl/verilog/register_file.v

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