OpenCores

URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_register_file.v] - Rev 217

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
202	Add DMA interface support + LINT cleanup	olivier.girard	3441d 07h	/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
180	Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme. Thanks to Sebastien Van Cauwenberghe's contribution :-)	olivier.girard	4297d 07h	/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
134	Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.	olivier.girard	4637d 08h	/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
132	Update FPGA examples with the POP.B bug fix	olivier.girard	4650d 08h	/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
130	Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 )	olivier.girard	4658d 07h	/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
117	To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license.	olivier.girard	4910d 09h	/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4944d 08h	/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	5020d 14h	/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
34	To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.	olivier.girard	5451d 09h	/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5451d 10h	/openmsp430/trunk/core/rtl/verilog/register_file.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5572d 12h	/openmsp430/trunk/core/rtl/verilog/register_file.v
17	Updated header with SVN info	olivier.girard	5598d 07h	/openmsp430/trunk/core/rtl/verilog/register_file.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5633d 07h	/openmsp430/trunk/core/rtl/verilog/register_file.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.