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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_sfr.v] - Rev 105

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Rev	Log message	Author	Age	Path
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	4922d 08h	/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
85	Diverse RTL cosmetic updates.	olivier.girard	4958d 01h	/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
34	To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.	olivier.girard	5353d 03h	/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5353d 04h	/openmsp430/trunk/core/rtl/verilog/sfr.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5474d 06h	/openmsp430/trunk/core/rtl/verilog/sfr.v
17	Updated header with SVN info	olivier.girard	5500d 01h	/openmsp430/trunk/core/rtl/verilog/sfr.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5535d 01h	/openmsp430/trunk/core/rtl/verilog/sfr.v

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