| Rev |
Log message |
Author |
Age |
Path |
| 180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4269d 06h |
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v |
| 154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4402d 07h |
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4609d 07h |
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v |
| 117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4882d 08h |
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4916d 07h |
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4972d 05h |
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4992d 13h |
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v |
| 85 |
Diverse RTL cosmetic updates. |
olivier.girard |
5028d 06h |
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v |
| 34 |
To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. |
olivier.girard |
5423d 08h |
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v |
| 33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5423d 09h |
/openmsp430/trunk/core/rtl/verilog/sfr.v |
| 23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5544d 11h |
/openmsp430/trunk/core/rtl/verilog/sfr.v |
| 17 |
Updated header with SVN info |
olivier.girard |
5570d 06h |
/openmsp430/trunk/core/rtl/verilog/sfr.v |
| 2 |
Upload complete openMSP430 project to the SVN repository |
olivier.girard |
5605d 06h |
/openmsp430/trunk/core/rtl/verilog/sfr.v |
