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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_watchdog.v] - Rev 99

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Rev	Log message	Author	Age	Path
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	5033d 18h	/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
34	To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.	olivier.girard	5423d 19h	/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5423d 20h	/openmsp430/trunk/core/rtl/verilog/watchdog.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5544d 21h	/openmsp430/trunk/core/rtl/verilog/watchdog.v
17	Updated header with SVN info	olivier.girard	5570d 17h	/openmsp430/trunk/core/rtl/verilog/watchdog.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5605d 17h	/openmsp430/trunk/core/rtl/verilog/watchdog.v

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