| Rev |
Log message |
Author |
Age |
Path |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4978d 07h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
5251d 08h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
5285d 07h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
5341d 06h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
5356d 07h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
5361d 13h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
5397d 05h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 67 |
Added 16x16 Hardware Multiplier. |
olivier.girard |
5724d 16h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 53 |
Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)
Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch. |
olivier.girard |
5763d 09h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 34 |
To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. |
olivier.girard |
5792d 09h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5792d 09h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5913d 11h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 17 |
Updated header with SVN info |
olivier.girard |
5939d 07h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
| 2 |
Upload complete openMSP430 project to the SVN repository |
olivier.girard |
5974d 06h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v |
