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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_defines.v] - Rev 102

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74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5203d 10h /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
72 Expand configurability options of the program and data memory sizes. olivier.girard 5230d 11h /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
67 Added 16x16 Hardware Multiplier. olivier.girard 5377d 18h /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
57 Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.		 olivier.girard 5411d 07h /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5445d 12h /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5566d 13h /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
17 Updated header with SVN info olivier.girard 5592d 09h /openmsp430/trunk/core/rtl/verilog/openMSP430.inc
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5627d 09h /openmsp430/trunk/core/rtl/verilog/openMSP430.inc

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