Rev |
Log message |
Author |
Age |
Path |
151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4463d 06h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4585d 08h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4858d 09h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
112 |
Modified comment. |
olivier.girard |
4891d 08h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4892d 08h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4948d 06h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4968d 14h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
74 |
Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly. |
olivier.girard |
5157d 08h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
72 |
Expand configurability options of the program and data memory sizes. |
olivier.girard |
5184d 09h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
67 |
Added 16x16 Hardware Multiplier. |
olivier.girard |
5331d 16h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
57 |
Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file. |
olivier.girard |
5365d 05h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5399d 10h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5520d 12h |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v |
17 |
Updated header with SVN info |
olivier.girard |
5546d 07h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.inc |
2 |
Upload complete openMSP430 project to the SVN repository |
olivier.girard |
5581d 07h |
/openmsp430/trunk/core/rtl/verilog/openMSP430.inc |