URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_defines.v] - Rev 64

Rev	Log message	Author	Age	Path
57	Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation. Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.	olivier.girard	5390d 00h	/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5424d 05h	/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5545d 06h	/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
17	Updated header with SVN info	olivier.girard	5571d 02h	/openmsp430/trunk/core/rtl/verilog/openMSP430.inc
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5606d 01h	/openmsp430/trunk/core/rtl/verilog/openMSP430.inc