OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_undefines.v] - Rev 190

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)		 olivier.girard 4269d 06h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4402d 07h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4609d 07h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4882d 08h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4916d 07h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4972d 05h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5181d 07h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
72 Expand configurability options of the program and data memory sizes. olivier.girard 5208d 08h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
67 Added 16x16 Hardware Multiplier. olivier.girard 5355d 15h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
57 Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.		 olivier.girard 5389d 04h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5423d 09h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.