URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_undefines.v] - Rev 77

Rev	Log message	Author	Age	Path
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5209d 13h	/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
72	Expand configurability options of the program and data memory sizes.	olivier.girard	5236d 14h	/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
67	Added 16x16 Hardware Multiplier.	olivier.girard	5383d 21h	/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
57	Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation. Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.	olivier.girard	5417d 10h	/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5451d 15h	/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v