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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [periph/] [template_periph_16b.v] - Rev 134

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134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4609d 12h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4882d 13h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4916d 12h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4972d 10h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4992d 18h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
66 The peripheral templates are now under BSD license.
Developers of new peripherals based on these templates won't have to disclose their code.		 olivier.girard 5356d 00h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5423d 14h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5544d 16h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
17 Updated header with SVN info olivier.girard 5570d 11h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5605d 11h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v

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