URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [periph/] [template_periph_16b.v] - Rev 72

Rev	Log message	Author	Age	Path
66	The peripheral templates are now under BSD license. Developers of new peripherals based on these templates won't have to disclose their code.	olivier.girard	5471d 08h	/openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5538d 22h	/openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5660d 00h	/openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
17	Updated header with SVN info	olivier.girard	5685d 19h	/openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5720d 19h	/openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v