OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [asm2ihex.sh] - Rev 207

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
207 Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) olivier.girard 3324d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
202 Add DMA interface support + LINT cleanup olivier.girard 3435d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3595d 23h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4587d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4631d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4938d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5228d 02h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5445d 03h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
17 Updated header with SVN info olivier.girard 5592d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5627d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.