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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [ihex2mem.tcl] - Rev 219

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106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 5010d 10h /openmsp430/trunk/core/sim/rtl_sim/bin/ihex2mem.tcl
17 Updated header with SVN info olivier.girard 5608d 11h /openmsp430/trunk/core/sim/rtl_sim/bin/ihex2mem.tcl
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5643d 11h /openmsp430/trunk/core/sim/rtl_sim/bin/ihex2mem.tcl

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