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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [msp430sim] - Rev 211

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207 Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) olivier.girard 3265d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
202 Add DMA interface support + LINT cleanup olivier.girard 3376d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3536d 23h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3937d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4449d 23h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4528d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4540d 10h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4572d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4741d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4879d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4960d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5169d 02h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
72 Expand configurability options of the program and data memory sizes. olivier.girard 5171d 02h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5328d 23h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5386d 03h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5507d 05h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
17 Updated header with SVN info olivier.girard 5533d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5568d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim

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